A reconfigurable architecture is understood to refer to modules (VPUs) having a configurable function and/or interconnection, in particular integrated modules having a plurality of arithmetic and/or logic and/or analog and/or storing and/or interconnecting modules (hereinafter referred to as PAEs) arranged in one or more dimensions and/or communicative peripheral modules (IO) interconnected directly or via one or more bus systems. PAEs may be of any embodiment or mixture and arranged in any hierarchy. This arrangement is referred to below as a PAE array or PA.
Generic modules of this type include systolic arrays, neural networks, multiprocessor systems, processors having multiple arithmetic units and/or logic cells, interconnecting and network modules such as crossbar switches, as well as known modules of the types FPGA, DPGA, XPUTER, etc. In this context, reference is made in particular to the following patents and applications by the present applicant: P 44 16 881.0-53, DE 197 81 412.3, DE 197 81 483.2, DE 196 54 846.2-53, DE 196 54 593.5-53, DE 197 04 044.6-53; DE 198 80 129.7, DE 198 61 088.2-53, DE 199 80 312.9, PCT/DE 00/08169, DE 100 36 627.9-33, DE 100 28 397.7, DE 101 10 530.4, DE 101 11 014.6, PCT/EP 00/10516, EP 01 102 674.7, PACT02, PACT04, PACT05, PACT08, PACT10, PACT11, PACT13, PACT21, PACT13, PACT18, PACT19, PACT16, PACT25, PACT27, PACT26/US, which are herewith incorporated to the full extent for the purpose of disclosure.